Synthesizing Recon gurable Sequential Machines Using Tabular Models

Two common problems we face in implementing recon gurable systems on currently available FPGA chips are: (1) tting designs which are too big for available hardware resources on a single FPGA chip, (2) lack of synthesis tools for high-level speci cations. One solution to address the rst problem is partial recon guration or run-time recon guration which requires only loading a portion of the design onto a FPGA chip at one time. In this paper, we present a synthesis methodology which starts from high-level system speci cations and synthesizes run-time recon gurable systems. Our approach uses tabular models as intermediate data structures. Tabular representations provide a convenient platform for separating control and data-path, and dividing the data-path into separate control-paths. This makes our approach very useful in synthesis targeted at implementations that depend on run-time recon guration to t bigger designs on currently available FPGA chips.